In modern integrated circuits and computer systems, increasing clock speed and high speed signal transitions are resulting in an increased need for accurate signal timings, communications, and system clock synchronization to allow for proper operation. For example, memory access speed and the resulting data transfer bandwidth has been a typical bottleneck in computer systems and other digital applications. A newer type of dynamic random access memory (DRAM), known as a synchronous DRAM or SDRAM, has been developed to provide faster operation and improve memory access times. SDRAMs are designed to operate synchronously with the system clock with input and output data synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices memory, access is still a limiting factor, and there is a need for still faster memory devices. With this in mind, double data rate (DDR) SDRAMs were developed to allow data transfers on both the rising and falling edges of the system data clock, providing twice the operating speed of the conventional SDRAM. Thus, DDR SDRAM provides up to twice as much data bandwidth as the conventional SDRAM for a given data clock. In addition, as with SDRAM, DDR SDRAMs are also capable of providing bursts of data at a high-speed data rate. It is noted that other synchronous memory types, including, but not limited to quad data rate (QDR), synchronous graphic DRAM (SGDRAM), DDR II SDRAM, and Rambus memory standards. It is further noted that other memory types, memory busses and memory interfaces, including, but not limited to, video RAM (VRAM), static RAM (SRAM), read only memory (ROM), electrically erasable programmable ROM (EEPROM), and Flash memory with both synchronous and asynchronous interfaces, are also well known in the art.
As system and integrated circuit clock frequencies increase, it is desirable to have less uncertainty in signal timings. For example, one such critical timing in modern computer systems is when valid data is available on the output of memory devices. In modern integrated circuits, clock synchronization and skew adjustment circuits (also known as clock recovery and/or duty cycle correction circuits) are commonly utilized to reduce this signal timing uncertainty by synchronizing with clock signals and/or other periodic signals and adjusting the signal delay and/or conditioning the signal itself. Such clock synchronization and skew adjustment circuits include, but are not limited to the digital delay locked loop (DLL), the synchronous mirror delay (SMD), and the duty cycle corrector (DCC). These circuits typically utilize large delay lines of multiple sequentially coupled delay elements to achieve their goal of synchronizing with and/or adjusting the duty cycle of an input periodic signal, such as a system clock. Because of this, the circuits can consume a large area of the integrated circuit die and consume significant amounts of power while in operation. In addition, as clock frequencies increase and signal timings become increasingly critical, the need for finer resolution in these clock synchronization and skew adjustment circuits is increasing. This in turn typically requires an increase in the number of the delay elements and a decrease in their individual time delay to achieve the required granularity in the delay lines utilized by these circuits. This is particularly an issue in integrated circuits that must operate over a wide range of clock frequencies in that the granularity of the delay lines and delay elements must be sized for the required resolution of the highest clock frequencies and yet be long enough to operated with/contain the slowest signals of the specified range of frequencies within the delay line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce clock synchronization and skew adjustment circuit size in integrated circuits and memory devices while maintaining adequate resolution.